(1) Field of the Invention
This invention relates to a method and apparatus for logic simulation used to verify an operation of a logic circuit, and more particularly to a method and apparatus for event driven logic simulation.
(2) Description of the Related Art
Generally, in event driven logic simulation apparatuses, a status change of a signal inputted/outputted to/from the I/O terminals of each element in the logic circuit to be simulated is defined as an event generation and is referred to as event data.
Each event data includes the following information:
1. event time data indicating when a signal status has changed, PA1 2. status change data indicating how a signal status has changed, PA1 3. element identification data identifying the element whose signal status has changed, and PA1 4. terminal identification data identifying the I/O terminals of the element whose signal status has changed. PA1 1. a fetch procedure: event data to evaluate is determined and then fetched from the storage unit. The event data fetched is struck off the storage unit. PA1 2. an evaluation procedure: a new signal status of the output terminal of an element indicated by the fetched event data is calculated. PA1 3. a transmission procedure: in response to the status change of the output terminal, new event data is generated which indicates a status change of the input terminal of an element connected with the above output terminal and then is stored in the storage unit. PA1 1. data for at least one event must be present for each input terminal of an element corresponding to the event data. PA1 2. the event time of the event data must be earlier than that of any other input terminals of the element.
The following three main procedures are repeated to simulate an operation of the logic circuit.
The following three different methods have been proposed as the above-mentioned fetch procedure to determine event data to be evaluated.